The article provides an in‑depth analysis of HPE’s latest Cray EX supercomputing platforms, detailing their GPU density, performance benchmarks, liquid‑cooling architecture, Slingshot 400 interconnect, upcoming storage solutions, and alternative ProLiant Compute XD servers for AI workloads.
This article analyzes a GPU‑based approximate nearest neighbor (ANN) retrieval solution built on NVIDIA's RAFT library, detailing algorithm selection, offline indexing tricks, batch online search design, performance results on a 25‑million‑vector workload, and cost‑saving implications for large‑scale search services.
The article examines the El Capitan supercomputer unveiled at SC24, detailing its AMD CPU‑GPU hybrid architecture, benchmark results, its dominance in the November 2024 Top500 list, and the broader implications for high‑performance computing, AI workloads, and the competitive landscape between AMD and NVIDIA.
This article examines how Baidu and NVIDIA leveraged the open‑source RAFT library to build a GPU‑accelerated approximate nearest neighbor (ANN) retrieval system, detailing algorithm choices, offline indexing, online batch processing, performance results, and practical guidelines for deploying ANN on GPUs.
Ant Group’s Computing Systems Lab announced that its GPU‑accelerated fully homomorphic encryption framework WarpDrive, which exploits Tensor and CUDA cores for high‑throughput NTT operations and parallel kernel designs, has been accepted as a paper at the IEEE HPCA 2025 conference.
The article analyzes the growing demand for high‑bandwidth, low‑latency GPU Scale‑Up interconnects in AI clusters, explains why existing Ethernet and RDMA solutions fall short, and examines the industry‑wide UALink alliance and Alibaba's Alink System as a new open‑ecosystem solution.
RTAMS‑GANNS, the award‑winning real‑time adaptive multi‑stream GPU system for online approximate nearest neighbor search, eliminates costly memory allocations and serial execution by using a dynamic memory‑block insertion algorithm and separate CUDA streams, cutting latency by 40‑80% and reliably serving over 100 million daily users in production.
The article introduces Intel's AI Flame Graph, a low‑overhead profiling tool that visualizes AI accelerator and GPU workloads across the full software stack, explains its design, demonstrates SYCL matrix‑multiply benchmarks, discusses challenges of AI instruction analysis, and outlines future adoption and impact.
The article introduces Intel’s AI Flame Graph, a low‑overhead profiling tool that visualizes AI accelerator and GPU execution alongside the full software stack, explains its design, shows SYCL matrix‑multiply examples, discusses challenges of AI workload analysis, and outlines future adoption and impact on performance and energy savings.
This tutorial walks programmers through preparing a GPU cloud environment, installing ComfyUI, downloading Flux1_dev models, integrating a custom LoRA, labeling generated images, and finally training the LoRA using ai‑toolkit, providing detailed commands, configuration tips, and practical cost estimates.
The Blackwell GB200 series delivers a massive leap in AI compute power with 20 petaFLOPS FP4 performance, a dual‑chip N4P design, 192 GB HBM3E memory, modular MGX servers, and advanced copper DAC and liquid‑cooling solutions that together boost training speed up to 30‑fold over the H100.
This article explains how Kubernetes manages and schedules GPU resources by introducing the Device Plugin framework, the Container Device Interface (CDI), Node Feature Discovery (NFD), and the GPU Operator, detailing their workflows, APIs, and practical usage with NVIDIA GPUs.
This article provides a comprehensive technical overview of modern GPU architecture, covering memory hierarchy, compute units, shader execution, rendering pipelines, and performance‑optimisation techniques such as unified shaders, SIMT, warp scheduling, and tile‑based rendering strategies.
This article details the design and optimization of Kola2d, a custom WebGL rendering engine for Docs online spreadsheets, explaining why WebGL was chosen, how the system separates business and rendering layers, and the many performance tricks that enable smooth 50+ FPS rendering of tables with up to a million cells.
This article explains the fundamental performance indicators of AI chips—TOPS, TFLOPS, and precision formats like FP16, FP32, and INT8—while comparing GPU, ASIC, and TPU architectures, highlighting Tensor Core advantages and TPU's superior efficiency over CPUs and GPUs.
The article explores Chris Lattner’s vision for Mojo—a Python‑compatible language designed for AI, GPU, and accelerator workloads—detailing its performance claims, SIMD support, complex‑number handling, and the growing developer community behind it.
At Computex 2024, AMD showcased its latest CPU, GPU, and AI‑accelerated technologies—including the high‑performance Zen 5 core, second‑generation XDNA NPU with 50 TOPS, the Ryzen 9000 consumer processor, the AI‑PC Strix Point platform, Versal AI Edge Gen 2, the upcoming MI‑series AI GPUs, and the new UA‑Link interconnect—highlighting the company’s roadmap for next‑generation computing and AI workloads.
The AI industry’s profit landscape mirrors a smile curve, with upstream GPU manufacturers and downstream application developers capturing most returns while costly large‑model R&D yields low margins, prompting predictions of GPU valuation corrections, a push for consumer‑facing killer apps, and massive application turnover through creative destruction.
The article analyzes the limits of the von Neumann model and Moore's law, explains how instruction set complexity defines processor categories, and argues that integrating CPUs, GPUs, FPGAs, DPUs and ASICs into a super‑heterogeneous ecosystem—driven by Intel, NVIDIA, ARM and emerging trends—will shape the future of computing through diverse workloads, AI demand, green efficiency and a global compute network by 2030.
This article explains the growing demand for high‑performance computing, introduces NVIDIA's Quantum‑2 InfiniBand platform with its high‑speed, low‑latency capabilities, provides a curated list of related technical articles, and offers an extensive Q&A covering compatibility, cabling, UFM, PCIe limits, and best‑practice deployment for AI and HPC workloads.
This article explains why single‑machine resources are insufficient for training ever‑larger language models, introduces the fundamentals of distributed training systems, details various parallel strategies such as data, model, pipeline, and hybrid parallelism, and provides practical PyTorch code and memory‑optimization techniques to accelerate large‑scale model training.
The article surveys open‑source GPU sharing and virtualization approaches for AI workloads, comparing soft isolation, CUDA‑level isolation, NVIDIA MPS, driver‑level isolation, GPU pooling and deep‑learning memory sharing, and highlights their architectures, isolation guarantees, and performance trade‑offs.
The article analyzes Nvidia’s accelerated GPU rollout, highlighting the Blackwell series’ massive performance and energy gains, the company’s AI‑focused Ethernet Spectrum‑X roadmap, and the broader impact on NVLink, InfiniBand, and Ethernet interconnects for upcoming massive AI clusters.
The article analyzes NVIDIA's DGX SuperPOD architectures across three GPU generations—H100, GH200, and GB200—detailing their NVLink/NVSwitch topologies, bandwidth calculations, scalability limits, and the practical challenges of constructing 256‑GPU and 576‑GPU supercomputing clusters.
While GPUs have driven AI acceleration for years, this article analyzes their architectural constraints, compares emerging alternatives such as Google's TPU and high‑end FPGAs, and explores future application niches like VR/AR, cloud gaming, and military systems where GPUs may still thrive or be replaced.
On the SM8650 platform, GLES issues synchronous and draw commands that the kernel‑mode driver translates into kgsl_drawobj structures, queues them in per‑context dispatch lists, processes fence, timestamp, and timeline syncpoints via dedicated kernel threads, and finally submits draw objects to the GPU firmware, with eglSwapBuffers triggering a fence syncpoint, a draw command, and a GPU fence creation.
This article breaks down the official and tested PC hardware requirements for Black Myth: Wu Kong, covering CPU, GPU, RAM, and ray‑tracing needs across 1080p, 2K, and 4K resolutions, and offers practical build recommendations for each performance tier.
This article provides a detailed technical overview of the Stream Multi‑processor (SM) in modern GPUs, explaining its micro‑architecture, instruction fetch‑decode pipeline, warp scheduling, SIMT stack handling, scoreboard mechanisms, and strategies for hiding memory latency to maximize parallel execution efficiency.
The PaddlePaddle Neural Network Compiler (CINN) combines a PIR‑based frontend that performs graph‑level optimizations such as constant folding, dead‑code elimination and operator fusion with a backend that applies schedule transformations and auto‑tuning, delivering up to 4× faster RMSNorm kernels and 30‑60% overall speed‑ups for generative AI and scientific‑computing workloads.
This guide walks you through deploying large language models with NVIDIA NIM on Volcengine's Kubernetes Engine (VKE), covering environment setup, model optimization, Helm chart deployment, monitoring integration, and the key advantages of using NIM as a cloud‑native AI micro‑service.
This article introduces cuDF, a Python GPU DataFrame library with a pandas‑like API, compares it to pandas, explains when to use cuDF versus Dask‑cuDF for single‑GPU or multi‑GPU workloads, and provides practical code examples for common data operations.
This article explains the essential metrics of AI chips—including TOPS and TFLOPS compute, precision formats like FP16, FP32 and INT8, and the roles of GPUs, ASICs and TPUs—while highlighting how Tensor Cores boost deep‑learning performance and comparing TPU efficiency to CPUs and GPUs.
This article examines the AI compute chip ecosystem, covering GPU, FPGA, and ASIC technologies, market share trends, key performance metrics such as TOPS, power and die area, and provides a detailed overview of major global and Chinese vendors and their flagship products.
The article reviews NVIDIA's newly released H20 AI accelerator for China, compares its performance and pricing with domestic chips, outlines the expanding Chinese AI chip ecosystem—including Huawei, Cambricon, HaiGuang, Alibaba, ByteDance, and Baidu—while highlighting market size growth, multi‑chip heterogeneity strategies, and the strong demand forecast through 2024.
The Venado supercomputer, unveiled at Los Alamos, combines Nvidia Grace CPUs, Hopper GPUs, HPE Slingshot interconnects, and massive memory bandwidth to achieve a 15.6‑petaflop FP64 peak, illustrating the evolving balance between CPU and GPU workloads in modern high‑performance computing.
This article walks through deploying the open‑source LLM serving tool Ollama and the Open‑WebUI interface on a Kubernetes cluster using Helm, covering GPU considerations, configuration files, service exposure, and model management with practical code examples.
This article reviews the principles and practical implementations of data, pipeline, tensor, sequence, and context parallelism together with memory‑saving strategies such as recomputation and ZeRO, and demonstrates how the QLM framework leverages these techniques to accelerate large‑model training and fine‑tuning on multi‑GPU clusters.
This guide explains how to deploy the open‑source LLM serving tool Ollama and the Open‑WebUI front‑end on a Kubernetes cluster using Helm charts, covering GPU configuration, persistent storage, service exposure, and model selection for large language models.
Nvidia plans to shorten its GPU generation cycle to one year, launching Blackwell Ultra in 2025, Rubin in 2026, and Rubin Ultra in 2027, while boosting token‑generation efficiency and introducing AI‑optimized Ethernet solutions like Spectrum‑X800, aiming to dominate large‑scale AI clusters and reshape the high‑performance networking market.
This article explains what a GPU is, how it differs from a CPU, its internal architecture, and why its massive parallel processing makes it essential for graphics rendering, scientific computation, and AI inference, illustrated with examples such as NVIDIA RTX 3090.
At Computex 2024 AMD showcased its latest Zen 5 CPU core, second‑generation XDNA NPU with 50 TOPS AI performance, the consumer‑grade Ryzen 9000 series, AI‑focused Strix Point processors, Versal AI Edge Gen 2, upcoming AI GPUs like MI325X/MI350/MI400, and the new UA‑Link 1.0 networking standard.
The article analyzes how generative AI models from GPT‑1 to the upcoming GPT‑5 are driving exponential growth in compute requirements, prompting massive cloud capital expenditures and intense competition among GPU vendors such as NVIDIA, AMD, Google, and emerging domestic chip makers, while also highlighting interconnect innovations and cost‑effective solutions.
The article analyzes Nvidia’s historic advantage, the massive performance and energy efficiency gains from Pascal to Blackwell GPUs, the economics of training large language models like GPT‑4, and the detailed roadmap of upcoming GPU, memory, and interconnect technologies shaping the future of data‑center AI.
The article analyzes Nvidia's latest AI‑focused hardware and software breakthroughs showcased at ComputeX 2024, detailing how GPU‑CPU hybrid architectures, new libraries, and high‑speed interconnects like NVLink dramatically boost performance while keeping power and cost growth modest.
This article compares Nvidia's NVLink (SXM) and PCIe GPU versions for AI servers, detailing their architectures, bandwidth, power consumption, and ideal use cases, helping readers choose the optimal configuration based on performance needs and budget constraints.
In just two weeks, engineer Adam Majmudar designed and implemented a minimalist GPU called tiny‑gpu—complete with a custom 11‑instruction ISA, Verilog RTL, and verified via OpenLane—sharing the open‑source project on GitHub, earning thousands of stars, and preparing it for fabrication through Tiny Tapeout 7, showcasing how modern tools make DIY chip design increasingly accessible.
This article introduces Numba, a Python just‑in‑time compiler, explains why it is advantageous over alternatives, demonstrates how to apply its @jit, @njit, @vectorize and other decorators, and shows how to run accelerated code on CPUs and GPUs using CUDA.
Nvidia’s latest Blackwell GPU, presented by Jensen Huang, promises unprecedented performance and energy efficiency for large‑scale AI models, while the company also showcases accelerated computing, NVLink interconnects, AI‑optimized DGX servers, the NIM platform for rapid LLM deployment, and ambitious projects such as Earth‑2 digital twins and next‑generation embodied AI robots.
HBM's near‑memory architecture, stacked design, and TSV integration dramatically cut latency and space while boosting bandwidth, leading NVIDIA and AMD to adopt it across multiple GPU generations, spurring fierce competition among SK Hynix, Samsung, and Micron and projecting a four‑fold market surge to $169 billion by 2024.
This guide explains how to efficiently deploy AI model inference services on Knative by externalizing model data, using Fluid for accelerated loading, configuring secrets, ImageCache, graceful shutdown, probes, autoscaling parameters, mixed ECS/ECI resources, shared GPU scheduling, and observability features to achieve fast scaling, low cost, and high elasticity.
The article explains how NCCL’s collective communication libraries enable efficient large‑scale model training by parsing GPU‑to‑NIC topology, forming flat‑ring and tree rings, improving logging and bandwidth metrics, detailing Ring AllReduce primitives, and proposing solutions to missing topology, metric, and mapping information for future optimization.
This article explains how GPUs, with their parallel architecture and extensive software ecosystem, have become essential for accelerating AI training and inference, outperforming CPUs and shaping the future of artificial intelligence across various industries.
This article provides a comprehensive technical overview of large‑scale GPU server architectures, detailing the component topology of 8‑GPU A100/A800 and H100/H800 nodes, explaining storage network cards, NVSwitch interconnects, bandwidth calculations, and the trade‑offs between RoCEv2 and InfiniBand for AI workloads.
This article explains the pivotal role of GPUs in today’s generative AI era, describes their architecture and applications, compares them with CPUs, ASICs, and FPGAs, and offers guidance on selecting the right processor for AI workloads while also noting related reference resources.
This article presents a comprehensive overview of Tencent PCG's GPU‑based recommendation model training framework, detailing why GPU adoption is essential, the hardware and software challenges faced, the multi‑level data architecture, pipeline design, and a series of network, storage, and compute optimizations, followed by future directions.
The article examines how the surge of generative AI (AIGC) is fueling rapid growth in AI server demand, detailing the emerging AIGC ecosystem, server hardware composition, model scaling, heterogeneous computing, training vs. inference workloads, market size forecasts, and the competitive landscape of AI server manufacturers.
This article details the migration of the Cloud Music desktop client from a legacy NEJ‑CEF hybrid to a React‑based architecture, outlines four major performance challenges, and explains the step‑by‑step optimizations—including API preloading, render memoization, virtual‑list replacement, and resource‑usage reductions—that cut startup latency by 48%, eliminated interaction stutter, and dramatically lowered CPU, GPU, and memory consumption.
The article analyzes why GPUs continue to dominate AI model training, comparing them with ASICs, CPUs, and other chips, and discusses ecosystem advantages, domestic development gaps, emerging edge‑AI demands, high‑bandwidth needs, and chiplet technology as future enablers.
This article explains the basic functions of CPUs and GPUs, their advanced capabilities and real‑world applications, and compares their architectures, processing models, and roles in environments such as IoT, mobile devices, Kubernetes, and AI workloads.
Nvidia’s next‑generation GeForce RTX 50 (Blackwell) GPUs are rumored to retain a 384‑bit memory bus, possibly adopt GDDR7 for up to 1.5 TB/s bandwidth, and push power consumption toward 1 kW, while Dell’s COO hints at new AI accelerators without liquid cooling.
This tutorial demonstrates how to train a MNIST digit‑recognition model using the Rust‑based Burn framework on top of the cross‑platform wgpu API, covering model export from PyTorch to ONNX, code generation, data loading, training loops, and performance comparison across CPU, GPU, and other backends.
This article explains how Remote Direct Memory Access (RDMA) technologies such as InfiniBand and RoCE bypass OS kernels to achieve ultra‑low latency and high bandwidth, discusses their hardware implementations, cost considerations, and their critical impact on large‑scale AI model training and HPC network design.
This article analyzes the factors influencing optical‑module requirements for AI GPU clusters, compares four typical network configurations for A100 and H100 SuperPODs, and provides step‑by‑step calculations that reveal the projected market demand for 200G, 400G, and 800G modules in 2023‑2024.
This article provides a detailed technical overview of modern multi‑GPU server architectures—including PCIe switches, NVLink, NVSwitch, and HBM—explaining their hardware topologies, bandwidth characteristics, monitoring methods, and network choices to help engineers design efficient AI training clusters.
The article analyzes the rapid evolution of AI servers, detailing the shift from general‑purpose to GPU‑enhanced AI hardware, the split between training and inference workloads, cost structures, forecasted compute needs for large models like GPT‑4, and the impact of US export restrictions and domestic competition on the global market.
Meituan Waimai’s search team built a GPU‑accelerated, mixed vector‑and‑scalar retrieval engine that supports billions of items, achieving over 99% recall and up to 89% latency reduction by combining pre‑filtering, optimized data layouts, multi‑GPU parallelism, and FP16 precision.
This article provides a detailed technical breakdown of modern multi‑GPU server nodes, covering component composition, storage network cards, NVSwitch interconnects, bandwidth calculations, and the architectural differences between NVIDIA A100/A800 and H100/H800 configurations for AI training workloads.
This article presents a comprehensive overview of large language model inference, describing the prefill and decoding stages, key performance metrics such as throughput, latency and QPS, and detailing a series of system-level optimizations—including pipeline parallelism, dynamic batching, KV‑cache quantization, and hardware considerations—to significantly improve inference efficiency on modern GPUs.
The article analyses NVIDIA’s new Blackwell platform, focusing on the GB200 NVL72 GPU and its 10 TB/s NVLink‑C2C interconnect, detailing massive training and inference speedups, rack‑level DGX SuperPOD architecture, copper‑cable trends, and the broader impact on AI‑driven data‑center workloads.
This article introduces Taichi, a Python‑embedded DSL that compiles kernel functions for CPU and GPU execution, and demonstrates through three practical examples how importing the library and adding decorators can accelerate Python code by up to a hundredfold, with detailed performance numbers and installation instructions.
FFmpeg provides a comprehensive, cross‑platform hardware acceleration framework that abstracts diverse GPU and dedicated video codec interfaces, defines HWContext types, device and frame contexts, and various codec configuration methods, enabling efficient video encoding, decoding, and filtering while addressing performance, compatibility, and pipeline complexity challenges.
The article analyzes the latest AI‑compute announcements from NVIDIA, AMD and Intel—including NVIDIA’s B200 GPU with 20 petaFLOPS FP4 performance, AMD’s MI300/MI400 roadmap, and Intel’s Gaudi 3 and Falcon Shores—while examining pricing, launch timelines, supply‑chain capacity, and the shifting market share among major cloud providers.
The article analyzes how the surge in AI workloads and the “East‑West Computing” strategy are reshaping the server industry, detailing the AI server component chain, the role of HBM memory, SSD evolution, and the stark cost‑structure differences between traditional and AI‑optimized servers.
This article compares NVIDIA's NVLink (SXM) and PCIe GPU versions for AI servers, detailing their architectures, bandwidth, power consumption, and ideal use cases, and provides guidance on selecting the right GPU based on workload size, flexibility, and cost considerations.
The GTC 2024 recap highlights Nvidia’s upcoming B100 and GB200 GPUs, their BlackWell architecture, performance breakthroughs, embodied‑intelligence initiatives, and the expanding AI application ecosystem across industries, offering a clear view of the next wave in accelerated computing.
Nvidia introduced the Blackwell GPU architecture at GTC, highlighting six breakthrough technologies, a 4nm process, massive performance gains, and its integration into DGX SuperPOD systems that promise to accelerate generative AI, data processing, and high‑performance computing across industries.
The article provides an in‑depth technical analysis of Nvidia’s NVLink C2C interconnect, comparing its latency, bandwidth, power efficiency, density and cost against traditional SerDes solutions and examining its role in building SuperChip architectures with Grace CPUs and Hopper GPUs.
The article analyzes current AI hardware options, explains why GPUs continue to dominate model training due to architectural compatibility, ecosystem support, and market maturity, and outlines emerging trends such as model miniaturization, optical interconnects, and chiplet technology that will shape the next generation of AI compute.
By fusing sparse‑feature operators, enabling multi‑stream execution, consolidating data copies, and merging inference batches, iQIYI reduced GPU CTR model latency to CPU‑level, boosted throughput over sixfold, and cut operational costs by more than 40%, overcoming launch‑overhead bottlenecks.
The new QQ 9.0 introduces aurora‑style animations generated by continuous, smoothed noise algorithms with uniform‑probability color mapping, and a spring‑driven 3D penguin rendered via Filament’s PBR materials and GPU compute shaders, achieving sub‑2 ms performance on most Android and iOS devices.
This guide shows how to quickly and cheaply deploy the open‑source Google Gemma large language model on Alibaba Cloud Function Compute GPU using the new idle‑billing mode, covering prerequisites, Docker image creation, function setup, idle reservation, testing, monitoring, and cost estimation.
The article recounts Yi Tay’s experience founding Reka and building large language models from scratch, highlighting the unpredictable quality of GPU clusters, the challenges of multi‑cluster orchestration, code‑base choices, and how startups must rely on fast, intuition‑driven experimentation to succeed.
This article explains how Kubernetes supports GPU workloads for AI and machine learning, covering device plugins, pod GPU requests, oversubscription, security isolation, cloud‑provider node setup, and protecting GPU nodes from non‑GPU pods.
Using Qualcomm’s Adreno GPU as a case study, the article explains how the Linux devfreq framework enables GPU frequency scaling by creating a kgsl devfreq device and an msm‑adreno‑tz governor, detailing their initialization, event handling, target‑frequency computation, and the kernel callbacks that apply the new rates.
This article provides a comprehensive technical overview of GPU architecture, from memory hierarchy and compute units to rendering pipelines and optimization techniques, explaining how modern graphics hardware processes shaders, manages resources, and balances performance across different rendering strategies.
This article presents a comprehensive overview of large language model inference, detailing the prefill and decoding stages, key performance metrics such as throughput, latency and QPS, and a series of system-level optimizations—including pipeline parallelism, dynamic batching, specialized attention kernels, virtual memory allocation, KV‑cache quantization, and mixed‑precision strategies—to improve GPU utilization and overall inference efficiency.
This article details Xiaohongshu's end‑to‑end GPU‑based transformation of its recommendation and search models, covering background, model characteristics, training and inference frameworks, system‑level and GPU‑level optimizations, compilation tricks, hardware upgrades, and future directions for large‑scale machine‑learning infrastructure.
This article provides a comprehensive overview of core AI concepts, from basic definitions of AI, AGI, and AIGC to detailed explanations of GPUs, major generative models, leading AI products, and influential companies, helping readers quickly grasp the landscape of AI-generated content.
The article examines how CPUs, GPUs, and memory have long formed the core of PC hardware, discusses the emerging role of NPUs for AI processing, and describes Intel's Lunar Lake strategy of integrating memory with the processor to deliver faster, lower‑latency performance in upcoming AI‑focused PCs.
The article outlines the 2024 computing‑power leasing industry framework, explains three main rental models, highlights the surge in demand driven by generative AI, the shortage of high‑end GPUs, and provides an extensive collection of links to reports and analyses on GPU technology, market dynamics, and future development paths.
This article explains how to efficiently deploy speech AI models—including ASR and TTS—on GPUs using NVIDIA's Triton Inference Server and TensorRT, covering background challenges, GPU‑based solutions, decoding optimizations, Whisper acceleration with TensorRT‑LLM, streaming TTS improvements, voice‑cloning pipelines, future plans, and a Q&A session.
The article analyzes the global CPU and GPU markets, showing Intel and AMD's overwhelming share, the rise of new data‑center players, key performance metrics for CPUs, the constraints of instruction‑set ecosystems, and emerging AI‑chip design trends that could open space for domestic Chinese manufacturers.
The article examines Nvidia's GH200 superchip and AMD's Instinct MI300, compares CPU, GPU, FPGA, and ASIC architectures, analyzes market share trends, and discusses opportunities for domestic chip makers in the rapidly evolving AI compute landscape.
This article introduces the Xinchuang (information technology innovation) industry, outlines its hardware components, and provides concise explanations of CPU concepts, instruction sets, GPU architecture and operation, as well as storage classifications, while also linking to related research reports and promotional resources.
2023 GPGPU research framework analysis reveals that while Chinese GPUs like BR100 and TianGai100 can match or exceed NVIDIA A100 in FP32, they still lag in FP64 and INT8 performance, and the domestic software ecosystem based on OpenCL trails far behind NVIDIA's CUDA, shaping short‑and‑term market dynamics.
Nvidia's RTX 5880 Ada, a China‑specific GPU built on a trimmed AD102 chip, offers 14,080 CUDA cores, 48 GB ECC GDDR6 memory, and an estimated 69.3 TFLOPS performance, positioning it between the RTX 6000 Ada and RTX 5000 Ada while complying with U.S. export limits.
The 2023 Xinchuang industry report outlines how China's information‑technology innovation sector entered a rapid growth phase, highlighting market expansion, dominant keywords, the evolving hardware ecosystem—including CPUs, GPUs, AI chips, DPU and cloud databases—and the strategic shift toward full‑industry adoption across eight critical sectors.
Due to U.S. export restrictions, NVIDIA released a China‑specific RTX 4090 D GPU that meets the TPP limit by reducing CUDA and Tensor cores while keeping most other specifications unchanged, and it is priced the same as the standard RTX 4090.
The article examines High Bandwidth Memory (HBM) technology—its 3D‑stacked architecture, superior bandwidth and power efficiency over GDDR, adoption in AI GPUs, generational performance gains, TSV manufacturing processes, and the evolving market share among major vendors.
This article compiles official specifications and benchmark data to compare Nvidia’s mainstream GPUs (L2, T4, A10, A10G, V100, A100, A800, H100) with Huawei’s Ascend series (910B, H20/L20), highlighting performance differences, inter‑GPU bandwidth via NVLink versus HCCS, and key takeaways for AI workloads.
