Overview of Modern Processor Instruction Set Architectures: x86, ARM, and RISC‑V

Modern processors mainly use two instruction set architectures (ISA): the CISC‑style x86 and the RISC‑style families such as ARM, MIPS, and RISC‑V.

CISC tries to accomplish complex tasks in a single instruction, offering high performance at the cost of higher power consumption.

RISC breaks tasks into simpler, smaller instructions, resulting in lower power usage but requiring more instructions to achieve the same work.

x86 can be divided into x86‑32 (Intel), x86‑64 (Intel) and AMD64 (AMD). RISC families include ARM, MIPS, Alpha, and RISC‑V. In China’s “information technology innovation” market, four technology paths (x86, ARM, MIPS, Alpha) and six major vendors (兆芯, 海光, 鲲鹏, 飞腾, 龙芯, 申威) have formed.

1. x86 Instruction Set

The x86 ISA maintains binary compatibility across generations, allowing programs for older chips to run on newer ones, which has driven the ISA to continuously expand with new instructions.

It also adopts a “strong instruction” design: a single instruction can perform complex operations (e.g., moving data between memory locations) within one clock cycle.

Intel’s statistics show that over nearly 40 years the x86 instruction count grew from fewer than 200 to more than 1,600.

The MOV instruction family illustrates how a single x86 instruction can encapsulate many micro‑operations.

Advantages and disadvantages of x86:

Binary compatibility makes hardware design complex but gave Intel a dominant PC market position.

Powerful single instructions reduce compiler complexity and simplify early assembly programming.

High‑efficiency parallel instructions boost single‑core performance.

Realizing CISC requires many redundant transistors, increasing die area and power consumption.

Today x86 dominates laptops, desktops, and servers, largely thanks to IBM’s early support.

2. ARM Instruction Set

Studies showed that about 80% of executed instructions belong to only 20% of the ISA; ARM removed the rarely used instructions, keeping a small, simple set.

ARM offers three licensing profiles:

Cortex‑A for high‑performance applications.

Cortex‑R for real‑time systems.

Cortex‑M for embedded devices.

Compared with x86, ARM’s RISC design:

Eliminates many redundant instructions.

Replaces a single powerful x86 instruction with several simple ARM instructions.

Consequences:

Simpler decoder hardware reduces area and power.

Each ARM instruction is weaker, lowering per‑instruction power.

More instructions are needed to achieve the same work, increasing compiler and assembly complexity.

ARM cores are smaller and consume less power, but individual cores are less performant, leading to multi‑core designs to match x86 performance.

3. RISC‑V Instruction Set

RISC‑V evolved from earlier RISC generations (RISC‑I to RISC‑IV) and has become a prominent open ISA, attracting both academic and commercial interest.

RISC‑V is expected to become the third major ISA after x86 and ARM, especially in IoT, but also gaining traction in PCs and servers. Key milestones in China include the formation of the China RISC‑V Industry Alliance (Sept 2018), the Open Instruction Ecosystem Alliance (Nov 2018), and several product launches by Alibaba‑Pingtouge, Zhaoyi, etc.

2018‑09: China RISC‑V Industry Alliance founded.

2018‑11: Open Instruction Ecosystem (RISC‑V) Alliance founded, chaired by Academician Ni Guangnan.

2019‑07: Alibaba’s “玄铁910” high‑performance RISC‑V processor released.

2019‑08: Zhaoyi released the world’s first 32‑bit general‑purpose RISC‑V MCU.

2020‑03: RISC‑V Foundation moved headquarters to Switzerland.

2023‑08: RISC‑V China Summit held in Beijing.

2023‑11: Alibaba launched three new “玄铁” series RISC‑V processors for mass production.

4. Instruction Set Summary

The choice between CISC (x86) and RISC (ARM, RISC‑V) is analogous to different cooking styles: one favors complex, feature‑rich instructions, the other favors simplicity and efficiency. Designers select the ISA based on application requirements, power budgets, and ecosystem considerations.

x86: Closed architecture, dominated by Intel and AMD; limited licensing.

ARM: Open‑licensed but requires royalty payments; widely adopted in China with both v8 and v9 licenses.

MIPS: Open, now largely superseded by RISC‑V.

Alpha: Historically open, now defunct.

RISC‑V: Fully open, free ISA with growing ecosystem and strong support from Chinese vendors.

For further reading, see the linked articles on IA‑64 vs x86‑64, the transition from x86 to ARM, and detailed industry reports.