The article explains how DPUs, as low‑power, high‑efficiency data‑processing units, complement CPUs and GPUs in modern data centers, reducing total cost of ownership while handling data movement, security, and analytics tasks more effectively than traditional processors.
This guide walks you through deploying the open‑source Stable Diffusion WebUI on Alibaba Cloud Function Compute using Serverless Devs, covering prerequisites, a single‑line deployment command, configuration details, access URL, and practical tips for handling GPU rendering and cold‑start latency.
This article explains why and how to fine‑tune the LLaMA‑7B model using the cheap Alpaca‑LoRA approach, covering hardware requirements, dataset preparation, LoRA training, optional model merging and quantization, and provides ready‑to‑run code snippets for single‑ and multi‑GPU setups.
This guide walks you through the prerequisites, step‑by‑step console and kubectl procedures, YAML configuration, and post‑deployment verification needed to run a CPU‑only Stable Diffusion model on Alibaba Cloud Container Service (ACK) and optionally switch to a GPU‑enabled version.
This article details the background, problems, and comprehensive refactoring plan for the xGis web‑based 3D map library, covering event classification, API design, layer interaction proxy, CPU/GPU picking implementations, performance trade‑offs, and future optimization directions.
This guide explains how to set up NVIDIA drivers, install the NVIDIA device plugin, and create a Kubernetes pod that requests GPU resources, providing step‑by‑step commands and a sample YAML manifest for GPU‑enabled workloads.
This article provides a comprehensive overview of GPU stream multiprocessors, detailing their micro‑architecture, instruction fetch‑decode‑execute pipeline, SIMT/ SIMD organization, warp scheduling, scoreboard mechanisms, and techniques for handling thread divergence and deadlock in GPGPU designs.
The article introduces PaddleBox and FeaBox, two GPU‑driven frameworks designed for massive sparse DNN training and unified feature extraction, detailing their architecture, performance advantages, hardware‑software co‑design challenges, and successful deployment across Baidu's advertising systems.
This article introduces Numba, a Just‑in‑Time compiler for Python that transforms functions into fast machine code using LLVM, explains why it lets you stay in pure Python, demonstrates basic @jit/@njit usage, advanced decorators, GPU execution with CUDA, and interoperability with C/C++ libraries.
PGLBox, Baidu’s GPU‑based large‑scale graph training framework, delivers up to 27× speedup over CPU clusters by fully GPU‑accelerating storage, sampling, and training, supporting billions of nodes, advanced GNN algorithms, multi‑level storage, and seamless integration of massive pretrained models.
Meituan Visual's engineering team tackled the common low‑GPU‑utilization bottleneck in online inference services by splitting model structures and adopting micro‑service deployment, raising GPU usage from 40% to 100% and more than tripling QPS, and then generalized the approach for other GPU‑based services.
The article analyzes how GPUs, once dominant in accelerating AI workloads, now face limitations in precision, energy efficiency, and on‑chip networking, prompting a shift toward specialized accelerators like Google's TPU and FPGA solutions, while also exploring emerging GPU‑friendly scenarios such as VR/AR, cloud gaming, and military applications.
This article explains GPU fundamentals, describing its role as a graphics‑oriented co‑processor, the reasons for using GPUs and other accelerators, the tasks they excel at and those they cannot handle, and outlines current market trends and architectural trade‑offs.
Facing memory leaks and high CPU load in a Canvas‑based avatar editor, the team switched to WebGL, leveraging GPU parallelism, off‑screen framebuffers, and blending techniques to dramatically reduce memory consumption and CPU usage while adding features like image layering and color blending.
These notes explain how GPUs address the massive data, serial dependencies, and high computational complexity of modern AI by employing three acceleration strategies—parallelism, operator fusion, and simplification—illustrated with Megatron-LM, MoE models, and practical compression techniques such as quantization, distillation, and pruning.
This article explains how GPUs address the massive data, serial dependencies, and high computational complexity of modern AI by employing three acceleration strategies—parallelism, operator fusion, and simplification—detailing methods such as model, pipeline, and tensor parallelism, Megatron framework, MoE models, and various model compression techniques.
This article demonstrates how importing the Taichi library into Python can dramatically accelerate compute‑intensive tasks, showcasing prime counting, longest common subsequence, and reaction‑diffusion simulations with speedups up to 120× and GPU support, while providing installation and usage guidance.
This article provides a comprehensive overview of the Xinchuang industry’s hardware fundamentals, detailing CPU architecture and operation, instruction set classifications, GPU concepts and workflows, storage categories, and the distinction between independent and integrated GPUs, while also noting related promotional resources.
The article provides a comprehensive technical overview of NVIDIA's Grace Hopper Superchip, detailing its heterogeneous CPU‑GPU design, high‑bandwidth NVLink‑C2C interconnect, performance advantages for HPC and AI workloads, programming model, and the architectural innovations that enable unprecedented scalability and productivity.
The article surveys GPU rendering pipelines and hardware architectures for desktop and mobile, explains classic stages, compares Immediate Mode, Tile‑Based and Tile‑Based Deferred rendering, details PowerVR, Mali and Adreno components, and offers optimization advice on draw calls, depth pre‑passes, shader efficiency, and render ordering.
This article introduces Numba, a Python Just-in-time compiler, explains why it is advantageous over alternatives, demonstrates how to apply its decorators such as @jit, @njit, @vectorize, and @cuda for CPU and GPU acceleration, and provides practical code examples and tips for optimal performance.
FastDeploy is an open‑source toolkit that standardizes AI model APIs and enables developers to deploy vision, NLP, and speech models on diverse hardware—including GPUs, CPUs, Jetson, ARM, and various NPUs—using just three lines of code or a single command, while delivering end‑to‑end performance optimizations.
The September 2022 China Database Industry Analysis report highlights a wave of hardware‑driven innovations—including multi‑core CPUs, heterogeneous GPUs/TPUs/DPU, programmable FPGAs, CXL‑DDR5, persistent memory, NVMe‑oF, and RDMA‑based storage—that enable massive data storage and high‑concurrency real‑time computing across a range of novel database architectures and products.
PaddleBox is Baidu’s GPU‑based ultra‑large‑scale sparse DNN training framework that combines a three‑tier hierarchical parameter server (SSD, DRAM, HBM) with pipelined scheduling and multi‑machine multi‑GPU communication, delivering 5–40× cost‑performance gains over traditional CPU solutions and powering Baidu’s advertising services.
ShaderNN is an open‑source, sub‑2 MB GPU‑shader inference engine that runs TensorFlow, PyTorch and ONNX models directly on mobile graphics textures via OpenGL fragment and compute shaders, delivering real‑time, low‑power AI for image‑heavy tasks while eliminating third‑party dependencies and achieving up to 90 % speed gains.
Koordinator v0.7 adds major cloud‑native scheduling features—including enhanced gang (coscheduling) with Strict/NonStrict modes, multi‑hierarchy ElasticQuota management, fine‑grained GPU resource protocols, richer diagnostic APIs, and safer descheduling—targeting machine‑learning and big‑data workloads on Kubernetes.
A team of three spent over ten months constructing a 1 Hz CPU, custom GPU, and complete game logic inside unmodded Minecraft using only redstone, enabling a playable 3D version of Minecraft within Minecraft itself.
This article explains the concept of OpenGL objects, focuses on common buffer objects such as VBO, VAO, and EBO, describes how they reduce CPU‑GPU transfer costs, and provides detailed code examples for creating, configuring, and rendering with Vertex Buffer Objects to improve graphics performance.
This article guides beginners through the fundamentals of computer graphics, explaining OpenGL, WebGL, GLSL, and the rendering pipeline, then demonstrates practical Three.js code for setting up scenes, cameras, lights, materials, and textures to create interactive 3D web experiences.
This article provides a comprehensive overview of NVIDIA's DOCA framework, BlueField DPU architecture, SDK components, programming models, and related technologies such as RDMA, RoCE, and GPUDirect RDMA, highlighting their roles in modern data‑center acceleration and security.
This article surveys the rapid growth of data‑center capacity, the rise of AI and big‑data workloads, and how emerging accelerators such as GPUs, DPUs, SmartNICs and heterogeneous CPU designs from Intel, AMD, Arm and Apple are reshaping server hardware and driving a new wave of performance and efficiency competition.
This article details NetEase Cloud Music’s four‑layer machine‑learning platform architecture, covering resource provisioning with Visual Kubelet and Alibaba Cloud ECI, Ceph storage optimizations, TensorFlow migration, large‑scale graph neural network support, and end‑to‑end workflow tooling that together enable efficient, cost‑effective AI development and deployment.
The OPR engine provides a cross‑platform, GPU‑accelerated rendering framework that unifies audio‑video pre‑ and post‑processing, native UI‑driven danmaku rendering, and real‑time visual effects such as human‑body recognition, using a modular command‑stream architecture, C++ core, monitoring tools, and extensibility for future Vulkan, VR, and plugin integration.
This article details Youku's technical approach to rendering bullet‑screen pass‑through on mobile devices, covering cloud‑based and on‑device segmentation pipelines, GPU‑accelerated rendering steps, performance optimizations, and engineering challenges to deliver seamless immersive viewing.
The Shopee Off‑Platform Ads team built a GPU‑accelerated Creative Rendering System that uses a four‑layer architecture, CGO‑bridged C/C++ kernels, and template caching to process billions of product images daily, achieving roughly ten‑fold speedup, half the cost, and far reduced rack space while handling high concurrency.
Recent analysis suggests that AMD’s upcoming top‑tier RDNA 3 GPU, the Navi 31, will abandon the rumored multi‑chiplet architecture in favor of a single, powerful compute die, reducing shader count and TFLOP ratings while still promising strong performance for gaming and data‑center workloads.
The article presents advanced OpenCL optimization techniques for Qualcomm Adreno mobile GPUs, explaining the programming model, profiling methods, bottleneck identification, and kernel‑level strategies such as fast math, fp16, vectorized memory accesses, and hardware‑specific features to improve compute‑ and memory‑bound performance on Android devices.
The article examines how GPUs have evolved from gaming accelerators to essential data‑center processors for AI, HPC, and scientific workloads, and compares the latest server‑grade offerings from Nvidia, AMD, and Intel—including performance specs, memory technologies, interconnects, and software ecosystems—highlighting the fierce competition shaping the future of compute.
NVIDIA has finally open‑sourced its Linux GPU kernel driver, a landmark move that promises tighter OS integration, easier debugging, and broader support for Turing and Ampere GPUs, while also reshaping the relationship between proprietary drivers, the Nouveau project, and major Linux distributions.
This article introduces WebGL fundamentals for frontend developers, explaining GPU versus CPU, GLSL shaders, and how JavaScript prepares data, followed by step‑by‑step code examples of fragment and vertex shaders, custom primitives, and using the gl‑renderer library to render graphics.
This article introduces WebGPU—a powerful yet still experimental web graphics API—showing how major frameworks like Three.js and Babylon.js adopt it for high‑performance 3D rendering, how TensorFlow.js leverages it for massive deep‑learning speedups, and provides hands‑on code examples from framework usage to raw WebGPU programming.
This guide explains PyTorch’s distributed training, contrasting single‑node DataParallel with multi‑node DistributedDataParallel, detailing essential parameters, group communication setup, proper use of DistributedSampler for data loading, handling IO bottlenecks, and avoiding common pitfalls such as memory imbalance, unsynchronized buffers, and unused‑parameter errors.
Based on recent leaks from 3DCenter.org and two prominent Twitter insiders, this analysis predicts launch windows, product codes, performance tiers, pricing pressures and power‑draw concerns for Nvidia’s upcoming RTX 4000 series and AMD’s RDNA 3 GPUs, while warning that the information remains speculative.
Based on recent leaks from 3DCenter.org and Twitter insiders Kopite7kimi and 暴龙兽55, the article forecasts Nvidia's Lovelace RTX 4000 series and AMD's RDNA 3 Navi 33/32 GPUs to launch between September 2022 and early 2023, analyzes their expected specifications, pricing dynamics, and potential market impact, and notes Intel's upcoming Arc cards as a wildcard.
This guide walks through setting up Docker on a Windows or Linux host, enabling Nvidia GPU support via the Container Toolkit, pulling a TensorFlow GPU image, launching a Jupyter Notebook server inside the container, and connecting it to Google Colab for deep‑learning training.
This article provides a detailed technical analysis of the leaked specifications for NVIDIA's Ada Lovelace GPU series, covering chip dimensions, L2 cache innovations, performance expectations, manufacturing node implications, and cost considerations while comparing them to AMD's offerings.
The article provides a comprehensive overview of AI chip technology, describing the dependence on mathematical models and semiconductor integration, classifying chips by architecture (GPU, FPGA, ASIC, SoC, brain‑like), deployment (cloud, edge, terminal), and outlining current challenges, market trends, and future research directions such as in‑memory and neuromorphic computing.
Chinese domestic GPU development has accelerated rapidly, driven by fast‑track product launches, strategic IP licensing from firms like Imagination Technologies, and supportive policies, while industry players navigate challenges of patents, design complexity, and market competition to bring full‑function GPUs to market.
This article explains how Google Cloud Vertex AI improves large‑scale distributed machine learning training performance by addressing the memory‑wall challenge with Fast Socket network stack enhancements for NCCL and a Reduction Server that accelerates gradient aggregation, delivering higher throughput and lower TCO for AI workloads.
This article explains OpenCL fundamentals, the Qualcomm Adreno GPU architecture, compatibility considerations, and practical optimization techniques—including profiling, bottleneck identification, and CPU‑to‑GPU conversion tips—to help developers write high‑performance mobile OpenCL code.
This article provides a thorough collection of commonly used PyTorch code snippets covering environment setup, reproducibility, GPU configuration, tensor manipulation, model building, data preprocessing, training and evaluation loops, custom loss functions, regularization techniques, learning‑rate scheduling, checkpointing, and practical tips for efficient deep‑learning development.
This article explains the fundamentals of high‑performance computing (HPC), covering its serial and parallel processing models, CPU and GPU roles, heterogeneous architectures, FLOPS performance metrics, market trends, and key terminology needed to grasp why HPC is essential for scientific and engineering simulations.
At the recent GTC event, NVIDIA introduced the H100 GPU built on the Hopper architecture using TSMC 4nm process, featuring 800 billion transistors, 16,896 CUDA cores, up to 700 W power, 3 TB/s memory bandwidth, and a specialized Transformer engine that accelerates large‑model training up to six times faster, alongside the Grace CPU Superchip and new AI supercomputing systems.
Offscreen rendering, a technique where the GPU or CPU renders content to a separate buffer outside the current screen framebuffer, can cause performance overhead due to buffer creation and context switches, and the article explains its principles, common trigger scenarios, and strategies to avoid it in iOS development.
This article explains the fundamentals of high‑performance computing (HPC), covering serial and parallel processing, CPU vs GPU roles, heterogeneous architectures, FLOPS performance metrics, system design challenges, and why HPC is essential for large‑scale scientific and engineering simulations.
The article provides a comprehensive overview of AI chips, explaining their broad and narrow definitions, core architectures such as GPU, FPGA, and ASIC, deployment scenarios from cloud to edge, training versus inference roles, current market dynamics, major vendors, and emerging application domains like autonomous driving and smart security.
The article provides a comprehensive overview of AI chips—including GPUs, FPGAs, and ASICs—their architectural distinctions, cloud and edge deployment models, market dynamics in China, and key application scenarios such as autonomous driving, smart security, and IoT devices.
Meituan’s delivery search and recommendation service migrated from separate CPU‑only models to a unified multi‑task model running on a heterogeneous CPU‑GPU architecture, applying system‑level placement, All‑On‑GPU lookup, FP16 mixed precision, operator fusion, TensorRT and TVM compilation, which together delivered roughly a four‑fold increase in inference throughput while maintaining cost.
The article outlines major trends influencing high‑performance computing, including AI integration, GPU/TPU advancements, flexibility in processor architectures, HPC‑as‑a‑Service, hybrid cloud solutions, democratization, the emergence of exascale systems, and micro‑architectural improvements, while providing links to related reports and resources.
This article analyzes the complexities of deploying machine‑learning models in production, outlines the limitations of the existing ABox architecture, and details a comprehensive cloud‑native redesign using Seldon on Kubernetes—including custom HDFS initializers, GPU management, logging, and resource monitoring—to streamline operations and enable unified CPU/GPU model serving.
The team replaced the cumbersome ABox deployment stack with Seldon‑based cloud‑native serving on Kubernetes, unifying TensorFlow and other framework models, adding GPU sharing, automated CRUD, per‑model ingress, monitoring, and log collection, achieving scalable, fault‑tolerant, zero‑downtime model deployment.
The article provides a comprehensive analysis of China's semiconductor challenges and progress, covering the status of domestic X86 processors, high‑speed ADC technology, automotive chip development, and GPU advancements, while highlighting market dynamics, licensing issues, and future prospects.
The paper presents a holistic algorithm‑system‑hardware co‑design for advertising deep‑learning inference, combining model pruning, approximate computing, kernel fusion, scheduling and PCIe transfer optimizations with GPU and NPU upgrades, achieving up to five‑fold speed‑up and significantly higher latency‑bounded QPS for large‑scale ad services.
dl_inference is an open‑source, production‑grade deep learning inference platform that supports TensorFlow, PyTorch and Caffe models, offering GPU and CPU deployment, TensorRT and MKL acceleration, multi‑node load balancing, and extensive Q&A on model conversion, hardware requirements, INT8 quantization, and performance gains.
This article introduces the Python libraries memory_profiler and Pytorch‑Memory‑Utils, demonstrates how to measure line‑by‑line CPU memory consumption and GPU memory usage in notebooks and scripts, and explains the additional overhead introduced by PyTorch during model loading.
XGBoost‑Ray provides a fault‑tolerant, multi‑node, multi‑GPU backend for XGBoost that integrates seamlessly with Ray Tune, supports distributed data loading, and can be enabled with only three code changes, enabling scalable training and inference on large clusters.
The 2021 China Integrated Circuit Market Research Report analyzes recent three‑year trends showing rising shares of MPU and logic chips, declining DRAM, stable analog and MCU, and details the market status, growth forecasts, and challenges for CPU, GPU, FPGA, ASIC, and storage technologies.
This article reveals the technical design of Youku's high‑performance danmaku rendering engine, covering its background, industry landscape, GPU‑based rendering pipeline, multi‑layer architecture, performance‑boosting techniques, real‑world benchmarks, and the innovative effects it enables.
The 2021 China Integrated Circuit Market Research Report analyzes recent three‑year trends, showing rising shares for MPU and logic chips, declining DRAM, stable analog and MCU, while detailing the market positions, growth rates, and challenges of CPU, GPU, FPGA, ASIC, and flash storage technologies.
The article analyzes how GPU architecture, originally designed for 3D graphics, is being reshaped by AI demands through specific‑domain designs, hardware/software interfaces, tensor acceleration, and 3D/AI convergence, ultimately arguing that GPUs will remain the central compute platform in the new golden age of computer architecture.
This article provides a comprehensive overview of GPU technology, covering its multi‑core architecture, market oligopoly among Intel, NVIDIA and AMD, classifications of integrated and independent GPUs, and the three major application trends of gaming performance, artificial intelligence/deep learning, and autonomous driving.
This article explores how various noise algorithms—including value, gradient, simplex, cellular, and FBM—are applied to short video visual effects, compares random number generators for GPU rendering, and provides GLSL code examples to illustrate implementation and performance trade‑offs.
The article walks through diagnosing why PyTorch cannot access the GPU, reinstalling CUDA, selecting matching PyTorch builds, adjusting versions, and verifying that CUDA becomes available for accelerated training.
This article explains how various noise algorithms—value, gradient, simplex, cellular, and FBM—are applied to short‑video visual effects, showcases shader implementations and image examples, and compares GPU random‑number generators to help developers choose the right balance of performance and visual quality.
The article analyzes why Flutter crashes on iOS when accessing the GPU in the background, explains the official SyncSwitch fix for ImageDecoder, and details Xianyu’s additional patches for MultipleFrameCodec, EncodeImage, and Rasterizer::DrawToSurface that together, via PR #28383, fully resolve the GPU‑background crash.
This article explains six practical techniques—parallel data loading, distributed multi‑GPU training, mixed precision, early stopping, sharded training, and inference optimizations—using PyTorch Lightning to dramatically accelerate deep‑learning pipelines, turning days‑long experiments into minute‑scale runs.
The article explains high‑performance computing (HPC) concepts, including serial and parallel processing, supercomputer performance measured in FLOPS, real‑world scientific applications such as drug discovery and weather forecasting, and the hardware architectures that enable these massive computational capabilities.
Meituan accelerates CTR model inference by fusing operators with TVM, optimizing CPU‑GPU data transfers, manually tuning high‑frequency subgraphs, and dynamically offloading workloads, achieving up to ten‑fold throughput gains on Tesla T4 GPUs while keeping latency stable and only modestly increasing beyond 128 QPS, though compilation remains slow and large‑model support needs improvement.
This article provides a comprehensive overview of GPUs, covering their history, architecture, processing workflow, and acceleration technologies such as CUDA and OpenCL, while comparing GPU and CPU designs and offering resources for further study.
This article introduces Google’s JAX library, covering its origins, core features such as automatic differentiation, JIT compilation, parallel and vectorized mapping, installation steps, code examples, and a comparative overview with TensorFlow and PyTorch for deep‑learning practitioners.
This guide walks you through installing NVIDIA drivers, CUDA, and nvidia-docker2 on a Linux host, configuring Docker to access the GPU, and verifying the setup with commands and sample TensorFlow/PyTorch code, enabling deep‑learning workloads inside containers.
The article reviews how deep learning models have grown deeper and wider, discusses the memory and bandwidth limits of single GPUs, and explains pipeline and sharding techniques—including GPU clusters and TPU pods—to efficiently train large‑scale models in industrial settings.
The article explains how artificial intelligence relies on algorithms, compute and data, compares engineering and simulation methods, and details the roles, architectures, performance and energy characteristics of GPUs, FPGAs, and ASICs as the primary hardware accelerators for modern deep‑learning applications.
This article explains how the CuPy library leverages NVIDIA CUDA GPUs to replace NumPy for array operations, provides installation steps, and presents benchmark code showing up to 700× speed improvements for large‑scale matrix computations compared to CPU‑based NumPy.
The article reviews the historical shift from CPU‑based ECUs to GPU‑centric and ASIC‑centric automotive processors, analyzes current GPU dominance, examines key industry players, and discusses why ASICs are expected to become the primary solution for future autonomous‑driving chips.
This FAQ summarizes practical guidance for participants of the 2021 Tencent Advertising Algorithm Competition on using the TI-ONE cloud notebook platform, covering instance initialization, resource switching, data handling, common errors, and Git integration.
This article introduces Numba, a Python just‑in‑time compiler, explains why it’s advantageous over alternatives, and provides detailed guidance on using its decorators such as @jit, @njit, @vectorize, and @cuda.jit, including code examples for CPU and GPU acceleration.
The article provides a comprehensive overview of GPU technology, its architecture, rapid market growth, segmentation by type, device and industry, cloud deployment trends, competitive landscape, and diverse applications ranging from high‑performance computing and AI to automotive, AR/VR, and IoT.
This week’s developer newsletter spotlights NASA’s open‑source‑based Ingenuity helicopter soaring on Mars, JD’s ESG report and green cloud initiatives, NVIDIA’s record‑breaking AI inference GPUs, rapid growth of China’s public‑cloud market, Tsinghua’s new chip academy, Hugging Face’s Accelerate library for multi‑GPU training, plus cutting‑edge research on GAN IP protection and hierarchical task learning presented at CVPR and ICLR.
This article explains how short‑video apps render text on the GPU by converting characters into GPU‑friendly primitives, covering image‑based text, triangulated glyphs, vector rendering extensions, and signed distance field methods, along with their advantages, drawbacks, and practical libraries.
This article examines how computing power has become a key production factor, detailing the shift from traditional CPUs and GPUs to specialized processors like DPUs, and explores emerging paradigms such as in‑memory, near‑memory, and edge computing that reshape data‑center architectures.
This article provides a comprehensive overview of NVIDIA's GPU architecture evolution—covering Fermi, Kepler, Maxwell, Pascal, Volta, Turing, and Ampere—detailing compute capabilities, SM structures, specialized units such as Tensor Cores, and their impact on AI and high‑performance computing workloads.
This report analyzes the evolution of processor chips, the rise of heterogeneous computing, and provides a comprehensive GPU investment logic framework, detailing GPU architecture, market competition, global industry landscape, and the challenges and prospects of domestic GPU development in China.
PyTorch 1.8, released by the PyTorch team, bundles over 3,000 commits since 1.7, introducing AMD ROCm support, enhanced Python function conversion, stable FFT and linear‑algebra APIs, complex‑tensor autograd, distributed‑training improvements, new mobile tutorials, performance tools, and several prototype features.
This article explains the role of GPUs in computing, traces the evolution of graphics standards and GPU architectures, and details the development of the Linux graphics stack from early X11 to modern Wayland, providing a comprehensive overview for developers and hardware enthusiasts.
This article documents a developer’s attempt to run Ethereum mining software on an M1‑based MacBook Air, detailing the required patches, compilation steps, observed hash rates, daily earnings, and how the performance compares with traditional GPU miners.
This article details the engineering challenges of serving a large BERT model in real‑time for 360 Search and describes a series of optimizations—including TensorRT‑based kernel fusion, model quantization, knowledge distillation, multi‑stream execution, caching, and dynamic sequence handling—that together achieve low latency, high throughput, and stable deployment on GPU clusters.
This article explains the fundamentals of parallel computing in the big‑data era, compares parallelism and concurrency, outlines GPU and distributed‑computing solutions, and provides a detailed guide to Python’s multiprocessing module with code examples, performance tests, and practical tips.
This guide walks you through installing NVIDIA drivers, CUDA, and nvidia-docker2 on a Linux host and configuring Docker containers to access the GPU, including verification steps and sample TensorFlow and PyTorch commands.
The article examines the rapid growth of data‑center workloads, explains why heterogeneous accelerators such as CPUs, GPUs, FPGAs and ASICs are needed, outlines evaluation standards, compares their compute performance and power efficiency, and discusses practical deployment cases and future trends.
