Sharing project experiences, insights into cutting-edge architectures, focusing on cloud computing, microservices, big data, hyper-convergence, storage, data protection, artificial intelligence, industry practices and solutions.
The article dissects the rise of GPU supernodes—large‑scale, rack‑level AI compute units—explaining the technical shift from scale‑up to scale‑out, the drivers behind industry adoption, the competing roadmaps of NVIDIA, Huawei and other Chinese vendors, and the practical implications for buyers.
The article explains why a single GPU can show multiple compute figures, clarifies the meanings of FLOPS, TOPS, precision levels and structured sparsity, demonstrates calculations with RTX 5090 and H100, and provides practical guidance for interpreting theoretical peaks versus real‑world performance.
The article explains HaiGuang’s Agent‑to‑Token open computing architecture, detailing how a dual‑chip CPU + DCU design enables end‑to‑end AI agent workflows, token generation, and secure, high‑performance compute through heterogeneous collaboration, open interconnects, and a full software stack.
Huawei’s Atlas 850E wind‑cooled supernode delivers 14.27 PFLOPS, 768 GB HBM, 4 TB/s bandwidth and VCE phase‑change cooling for inference in standard data centers, while the Atlas 950 SuperPoD provides a flagship 1 EFLOPS FP8 training platform with 256 TB unified memory, 1.72 PB/s interconnect, sub‑3 µs RTT, full liquid cooling and scalability up to 8 192 NPU cards.
At Hot Chips 2026, Samsung, SK Hynix and Micron warned that traditional HBM is nearing physical limits and outlined a three‑stage roadmap that moves from stacking to integrated Base‑Die, while d‑Matrix showcased a 3D‑DRAM solution delivering ~100 TB/s bandwidth but with limited capacity, highlighting packaging and power challenges as the next competitive frontier.
The article dissects a network switch to reveal its core ASIC, PHY chips, packet buffer, CAM‑based MAC address table, CPU and management ports, then follows a data frame through learning, table lookup, and forwarding decisions—including unicast, unknown‑unicast flood, broadcast/multicast flood and filtering—while noting advanced features such as static MAC entries and MAC‑migration suppression.
The article breaks down the 2026 CPU market into four performance tiers, comparing Intel and AMD flagship, mid‑range, mainstream and entry‑level processors with benchmark data, explaining which models excel in gaming, productivity or budget scenarios and offering concrete buying recommendations.
Nvidia has warned core customers that rising high‑bandwidth memory (HBM) costs will push prices of its Grace Blackwell and next‑gen Vera Rubin AI servers up by more than 15%, a hike that is already affecting major cloud providers, driving up server and compute‑as‑a‑service fees and prompting cloud vendors to accelerate their own chip development.
The 2026 storage‑chip market report analyzes how exploding AI compute demand drives a historic surge in high‑bandwidth memory, enterprise SSD and DDR5 prices, projects global sales to reach $2.23 trillion by 2025, and details shifting market shares among Samsung, SK Hynix, Micron and rising Chinese players such as Yangtze Memory and ChangXin.
This article walks through the entire chip design process—from silicon material and doping, through logic gates and processor building blocks, to hierarchical design flow, layout planning, multi‑metal interconnects, and the impact of photolithography on yield—while offering a downloadable PDF reference.
