Sharing project experiences, insights into cutting-edge architectures, focusing on cloud computing, microservices, big data, hyper-convergence, storage, data protection, artificial intelligence, industry practices and solutions.
This report analyzes how the convergence of Moore's law slowdown and large‑model scaling laws creates a feedback loop between compute power and intelligence, driving the emergence of AI‑specific chips, high‑speed networking, and DPU architectures that together reshape modern AI infrastructure.
Huawei’s 2025 Full‑Connection Conference unveiled the Atlas 950 and Atlas 960 SuperPoD supernodes, detailing their massive card counts, unprecedented compute, memory and bandwidth capabilities, and explaining how their full‑stack hardware‑software design dramatically accelerates large‑model AI training and inference.
Nvidia's Rubin CPX GPU, unveiled in September 2025, uses GDDR7 memory and a split‑stage architecture to dramatically boost token‑per‑second rates for long‑context inference, while its integration into third‑generation Oberon servers promises higher power density, improved ROI, and scalable data‑center deployments.
Large‑scale AI model training now demands unprecedented bandwidth and latency performance, forcing data centers to adopt three scaling approaches—Scale‑up, Scale‑out, and Scale‑Across—while leveraging optical I/O, CPO, and optical circuit switching to overcome power, distance, and bandwidth limits.
This article explains the types of AI compute chips, their market share and key performance metrics, details Nvidia's GPU architecture, and surveys the emerging Chinese AI chip manufacturers and their flagship products, providing a comprehensive overview of the AI hardware landscape.
The article examines the limitations of traditional von‑Neumann CPUs and power‑hungry GPUs for modern AI workloads, explains the rise of ASIC and FPGA based AI accelerators, compares major industry solutions, and highlights why reconfigurable, low‑power AI chips are becoming essential for robotics and edge computing.
This article examines the differences between Scale‑Out and Scale‑Up networking in AI compute clusters, comparing PCIe, Ethernet, InfiniBand, NVLink, UALink, and emerging standards like UB‑Mesh, and explains how each technology impacts bandwidth, latency, scalability, and cost for large‑scale model training.
The article analyzes Nvidia's 2023 Blackwell GPU series and GB200 NVL72 architecture, detailing their advanced 3‑4nm manufacturing, redesigned CUDA cores, next‑gen ray‑tracing and DLSS upgrades, massive compute and memory bandwidth gains, NVLink Gen5 improvements, and the diverse GB200 product configurations for high‑performance AI workloads.
Huawei’s Da Vinci AI architecture, introduced with the Kirin 810 SoC, combines a 3D Cube matrix‑multiply engine, vector and scalar units, and flexible scaling to deliver high‑performance, energy‑efficient AI compute across devices from low‑power IoT to high‑end cloud servers.
The article examines the soaring electricity demand of data centers worldwide, especially in China, highlights regional distribution and PUE improvements, explores AI's massive power consumption, and outlines green computing strategies such as efficiency upgrades, waste‑heat reuse, and renewable energy integration.
