Sharing project experiences, insights into cutting-edge architectures, focusing on cloud computing, microservices, big data, hyper-convergence, storage, data protection, artificial intelligence, industry practices and solutions.
The article outlines the upcoming high‑bandwidth memory (HBM) generations—from HBM4 to HBM8—detailing their planned release years, data rates, bandwidth, capacity, architectural innovations, and the shift toward memory‑centered computing for AI and high‑performance workloads.
This article provides a comprehensive overview of ASIC technology, covering its definition, origins, design process, key parameters, core techniques, and major application domains such as data centers, AI, automotive, and more, while also comparing it to general‑purpose ICs and highlighting leading industry players.
The article examines CXL interconnect chips—high‑speed, low‑latency devices built on the Compute Express Link protocol—covering their technical fundamentals, supportive policies, industry chain, booming Chinese server market demand, global market forecasts, competitive landscape, and future trends driven by AI and data‑center workloads.
China’s computing‑power industry is rapidly maturing as national policies, massive infrastructure investments, and domestic chip development converge to create a strategic high‑ground that fuels AI, data centers, and digital‑economy transformation, with clear upstream, mid‑stream, and downstream value chains.
This article provides a comprehensive overview of PCIe interconnect chips, covering their definition, industry classification, development history, policy support, supply‑chain structure, Chinese server market growth, global market size and forecasts, product composition, competitive landscape, and future trends toward higher speeds and lower latency.
This article explains how Chiplet technology boosts integration and performance in modern SoCs, compares MCM, CoWoS, and EMIB packaging methods, discusses architectural design strategies and the UCIe standard, and highlights real‑world examples from Intel, AMD, Huawei, and Apple.
The article explains how AI‑driven data center networks must handle massive distributed workloads, why traditional Ethernet falls short, and how NVIDIA’s Spectrum‑X Ethernet and Quantum InfiniBand use loss‑less RDMA, dynamic routing, advanced congestion control, and hardware‑accelerated collective communication to deliver the bandwidth, latency, and scalability required for generative AI and large‑scale model training.
The article explains the architecture of enterprise SSDs, compares SATA, SAS and PCIe interfaces, highlights the performance gap between enterprise and consumer SSDs, presents global and Chinese market growth forecasts, and discusses how AI, cloud computing and domestic innovation are driving rapid evolution and adoption of high‑performance storage solutions.
The article details Huawei’s CloudMatrix384 AI supernode, describing its 384 Ascend 910C NPUs, 192 Kunpeng CPUs, ultra‑high‑bandwidth UB network, three complementary network planes (UB, RDMA, VPC), and the non‑blocking topology that enables sub‑microsecond inter‑node latency across a 16‑rack deployment.
The article explains how AI large‑model training demands massive GPU resources and how carefully designed network architectures—such as Clos/Fat‑Tree, Spine‑Leaf, multi‑rail versus single‑rail connections, Dragonfly, and Torus—impact performance, scalability, cost, and reliability, guiding the selection of optimal data‑center networks.
